FIG. 1 is an illustration of a conventional four transistor (4T) imager pixel 100 typically used in a CMOS imager. The pixel 100 includes a light sensitive element 101, shown as a photodiode, a floating diffusion charge storage node C, and four transistors: a transfer transistor 111, a reset transistor 112, a source follower transistor 113, and a row select transistor 114. The pixel 100 accepts a TX control signal for controlling the conductivity of the transfer transistor 111, a RST control signal for controlling the conductivity of the reset transistor 112, and a ROW control signal for controlling the conductivity of the row select transistor 114. The voltage at the floating diffusion node C controls the conductivity of the source follower transistor 113. The output of the source follow transistor 113 is presented at node B when the row select transistor 114 is conducting.
The states of the transfer and reset transistors 111, 112 determine whether the floating diffusion node C is coupled to the light sensitive element 101 for receiving photo-generated charge generated by the light sensitive element 101 during a charge integration period, or a source of pixel power VAAPIX from node A during a reset period.
The pixel 100 is operated as follows. The ROW control signal is asserted to cause the row select transistor 114 to conduct. At the same time, the RST control signal is asserted while the TX control signal is not asserted. This couples the floating diffusion node C to the pixel power potential VAAPIX at node A, and resets the voltage at node C to the pixel power potential VAAPIX, less a voltage drop associated with reset transistor 112. The pixel 100 outputs a reset signal Vrst at node B. As will be explained in greater detail below in connection with FIG. 2, node B is typically coupled to a column line 215 (FIG. 2) of an imager 200.
While the transistor 111 is off, the light sensitive element 101 is exposed to incident light and accumulates charges based on the level of the incident light during a charge integration period. After the charge integration period and after the RST control signal is off, thereby turning off reset transistor 112, the TX control signal is asserted. This couples the floating diffusion node C to the light sensitive element 101. Charge flows through the transfer transistor 111 and diminishes the voltage at the floating diffusion node C in accordance with the accumulated charge. The pixel 100 thus outputs a photo signal Vsig at node B.
FIG. 2 is an illustration of an imager 200 that includes a plurality of pixels 100 forming a pixel array 201. Due to space limitations the pixel array 201 is drawn as a 4 row by 4 column array in FIG. 2. One skilled in the art would recognize that most imagers 200 would ordinarily include many more pixels 100 in the array. The imager 200 also includes row circuitry 210, column circuitry 220, a digital processing circuit 240, and a storage device 250. The imager 200 also includes a controller 260, for controlling operations of the imager 200.
The row circuitry 210 selects a row of pixels 100 from the pixel array 201. The pixels 100 in the selected row output their reset and pixel signals Vrst, Vsig to the column circuitry 220, via column output lines 215, which samples and holds the reset and pixel signals Vrst, Vsig for each pixel in a row. The rows are activated one by one in sequence to send successive row signals to column lines 215.
The column circuitry 220 is responsible for converting the pixel reset Vrst and photo Vsig signals into digital values that can then be further processed in the digital domain. In order to do this, the column circuitry 220 samples and holds the reset Vrst and photo Vsig signals produced by each pixel. An analog pixel output signal Vpixel is formed as the difference between the reset Vrst and photo Vsig signals, i.e., Vpixel=Vrst−Vsig. The pixel output signal Vpixel is then converted into a digital value. Imager 200 uses a column parallel architecture, in which the outputs of several pixels 100 in the selected row are simultaneously sampled and held, and converted to digital values.
The digital values are output to the digital processing circuit 240, which performs image processing on the digital values to produce a digital image. The processed digital values are stored in the storage device 250.
The controller 260 is coupled to the pixel array 201, row circuitry 210, column circuitry 220, and storage device 250, and provides control signals to perform the above described processing.
FIG. 3 is a more detailed illustration of the column circuitry 220. The column circuitry 200 comprises a plurality of identical signal chains 301a, 310b. Each signal chain 301a, 301b is coupled to two column output lines 215 from the pixel array 201 (FIG. 2). The column output lines 215 are coupled to a multiplexer 310, which is used to select the signals on one of the two column output lines 215 for subsequent processing.
The first processing stage after the multiplexer 310 is an analog processor circuit 320. The analog processor circuit 320 is used to sample and hold the reset Vrst and photo Vsig signals. Once both signals Vrst, Vsig have been sampled and held, the analog pixel output signal Vpixel can be formed as the difference (Vrst−Vsig) of the two analog signals Vrst, Vsig.
The next processing stage is an analog gain stage 330, which conditions the analog signal to a suitable level to be used as an input signal to an analog-to-digital converter (ADC) 340.
The analog-to-digital converter 340 converts the analog Vpixel signal into a corresponding digital value.
The digital value is routed to a demultiplexer 350, and stored in one of the digital storage locations 360 in the signal chain 301a, 301b. The digital storage locations 360 can be read by the digital processing circuit 240 (FIG. 2) to further process the pixel signals in the digital domain.
In the column circuitry 220, the above described processing is performed once for each column output line 215 coupled to each signal chain 301a, 301b. For example, since FIG. 3 illustrates an example circuit 220 where each signal chain 301a, 301b is coupled to two column output lines 215, each signal chain 301a, 301b performs the above described processing twice for each row readout operation. That is, the above described processing is performed in each of the signal chains 301a, 301b a first time for a first one of the column output lines 215 and a second time for a second one of the column output lines 215. The multiplexer 310 and demultiplexer 350 are thus set to respectively select a first one of the two column output lines 215 and storage locations 360, and then select a second one of the two column output lines 215 and storage locations 360.
Although each signal chain 301a, 301b of the column circuitry 220 is designed to have the identical response, different signal chains 301a, 310b are likely to have non-identical responses due to variations inherent in semiconductor fabrication, which may be seen as noise in the images produced by the imager 200 (FIG. 2). Accordingly, there is a need and desire to economically and quickly calibrate multiple signal chains in the column circuitry of an imager to compensate for any variations between the chains.